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DFT
2007
IEEE
103views VLSI» more  DFT 2007»
14 years 2 months ago
Lazy Error Detection for Microprocessor Functional Units
We propose and evaluate the use of lazy error detection for a superscalar, out-of-order microprocessor’s functional units. The key insight is that error detection is off the cri...
Mahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J...
SAC
2006
ACM
14 years 2 months ago
Branchless cycle prediction for embedded processors
Modern embedded processors access the Branch Target Buffer (BTB) every cycle to speculate branch target addresses. Such accesses, quite often, are unnecessary as there is no branc...
Kaveh Jokar Deris, Amirali Baniasadi
WCAE
2006
ACM
14 years 2 months ago
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis
Two of the most important design issues for modern processors are power and performance. It is important for students in computer organization classes to understand the tradeoff b...
Clint W. Smullen, Tarek M. Taha
HPCA
2000
IEEE
14 years 27 days ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri