918 search results - page 3 / 184 » Speculative Issue Logic |
JILP
2000
13 years 10 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
MICRO
1993
IEEE
14 years 3 months ago
1993
IEEE
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
GLVLSI
2003
IEEE
14 years 4 months ago
2003
IEEE
It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a res...
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
Energy dissipation from the issue queue and register file constitutes a large portion of the overall energy budget of an aggressive dynamically scheduled microprocessor. We propo...