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DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
ICPP
2002
IEEE
14 years 17 days ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
MICRO
1994
IEEE
96views Hardware» more  MICRO 1994»
13 years 11 months ago
A fill-unit approach to multiple instruction issue
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...
Manoj Franklin, Mark Smotherman
ICDE
2002
IEEE
117views Database» more  ICDE 2002»
14 years 9 months ago
Exploring Aggregate Effect with Weighted Transcoding Graphs for Efficient Cache Replacement in Transcoding Proxies
This paper explores the aggregate effect when caching multiple versions of the same Web object in the transcoding proxy. Explicitly, the aggregate profit from caching multiple ver...
Cheng-Yue Chang, Ming-Syan Chen
SIGCOMM
1998
ACM
13 years 12 months ago
Summary Cache: A Scalable Wide-Area Web Cache Sharing Protocol
Abstract—The sharing of caches among Web proxies is an important technique to reduce Web traffic and alleviate network bottlenecks. Nevertheless it is not widely deployed due to ...
Li Fan, Pei Cao, Jussara M. Almeida, Andrei Z. Bro...