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IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 7 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....
LCTRTS
2009
Springer
14 years 2 months ago
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
APLAS
2004
ACM
14 years 27 days ago
Concurrency Combinators for Declarative Synchronization
Developing computer systems that are both concurrent and evolving is challenging. To guarantee consistent access to resources by concurrent software components, some synchronizatio...
Pawel T. Wojciechowski
AINA
2009
IEEE
14 years 17 days ago
A Generic Database Web Service for the Venice Service Grid
This work describes a generic database service for the lightweight Venice Service Grid, which has been developed at the University of Kaiserslautern, Germany. By using Web service...
Michael Koch, Markus Hillenbrand, Paul Müller