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HPCA
2006
IEEE
14 years 8 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
PDPTA
2000
13 years 9 months ago
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures
The paper focuses on coarse-grained dynamically reconfigurable array architectures promising performance and flexibility for different challenging application areas, e. g. future ...
Jürgen Becker, Manfred Glesner, Ahmad Alsolai...
ICS
2003
Tsinghua U.
14 years 23 days ago
Reducing register ports using delayed write-back queues and operand pre-fetch
In high-performance wide-issue microprocessors the access time, energy and area of the register file are often critical to overall performance. This is because these pararmeters g...
Nam Sung Kim, Trevor N. Mudge
DCOSS
2010
Springer
14 years 11 days ago
A Novel Mobility Management Scheme for Target Tracking in Cluster-Based Sensor Networks
Abstract. Target tracking is a typical and important application of wireless sensor networks (WSNs). In the consideration of scalability and energy efficiency for target tracking ...
Zhibo Wang, Wei Lou, Zhi Wang, Junchao Ma, Honglon...
IPPS
2000
IEEE
13 years 12 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather