Sciweavers

2020 search results - page 259 / 404
» Speeding up Slicing
Sort
View
ICPP
2003
IEEE
14 years 3 months ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta
INFOCOM
2003
IEEE
14 years 3 months ago
Turning Heterogeneity into an Advantage in Overlay Routing
Abstract— Distributed hash table (DHT)-based overlay networks, represented by Pastry, CAN, and Chord, offer an administration-free and fault-tolerant application-level overlay ne...
Zhichen Xu, Mallik Mahalingam, Magnus Karlsson
PDP
2003
IEEE
14 years 3 months ago
A Parallel Evolutionary Algorithm for Circuit Partitioning
As general-purpose parallel computers are increasingly being used to speed up different VLSI applications, the development of parallel algorithms for circuit testing, logic minimi...
Raul Baños, Consolación Gil, Maria D...
PG
2003
IEEE
14 years 3 months ago
Hierarchical Least Squares Conformal Map
A texture atlas is an efficient way to represent information (like colors, normals, displacement maps ...) on triangulated surfaces. The LSCM method (Least Squares Conformal Maps...
Nicolas Ray, Bruno Lévy
PADS
2003
ACM
14 years 3 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper