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    » Speeding up power estimation of embedded software
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    VLSID
    2007
    IEEE
    152views VLSI» more  VLSID 2007»
    An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
    14 years 7 months ago
    An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect
    Download  www-unix.ecs.umass.edu
    With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
    Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip K...
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    JCP
    2008
    216views more  JCP 2008»
    Design Overview Of Processor Based Implantable Pacemaker
    13 years 7 months ago
    Design Overview Of Processor Based Implantable Pacemaker
    Download  www.academypublisher.com
    Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
    Santosh D. Chede, Kishore D. Kulat
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    JIB
    2008
    76views more  JIB 2008»
    WebStruct and VisualStruct: web interfaces and visualization for Structure software implemented in a cluster environment
    13 years 7 months ago
    WebStruct and VisualStruct: web interfaces and visualization for Structure software implemented in a cluster environment
    Download  journal.imbio.de
    Structure, is a widely used software tool to investigate population genetic structure with multi-locus genotyping data. The software uses an iterative algorithm to group individua...
    B. Jayashree, S. Rajgopal, David A. Hoisington, V....
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    CASES
    2001
    ACM
    113views System Software» more  CASES 2001»
    Application specific architectures: a recipe for fast, flexible and power efficient designs
    13 years 11 months ago
    Application specific architectures: a recipe for fast, flexible and power efficient designs
    Download  www.eecs.umich.edu
    The general purpose processor has long been the focus of intense optimization efforts that have resulted in an impressive doubling of performance every 18 months. However, recent ...
    Christopher T. Weaver, Rajeev Krishna, Lisa Wu, To...
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    CGO
    2005
    IEEE
    155views Software Engineering» more  CGO 2005»
    Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
    14 years 1 months ago
    Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
    Download  cccp.eecs.umich.edu
    Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
    Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
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