178 search results - page 27 / 36 » Splitting a CR-Prolog Program |
ICALP
2009
Springer
14 years 8 months ago
2009
Springer
Abstract In a load balancing network each processor has an initial collection of unit-size jobs, tokens, and in each round, pairs of processors connected by balancers split their l...
SIGMOD
2008
ACM
14 years 8 months ago
2008
ACM
We present a novel design and implementation of relational join algorithms for new-generation graphics processing units (GPUs). The most recent GPU features include support for wr...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
14 years 4 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
CGO
2010
IEEE
14 years 2 months ago
2010
IEEE
Decoupled Software Pipelining (DSWP) is one approach to automatically extract threads from loops. It partitions loops into long-running threads that communicate in a pipelined man...
CEC
2008
IEEE
14 years 2 months ago
2008
IEEE
—Genetic programming (GP), is a very general and efficient technique, often capable of outperforming more specialized techniques on a variety of tasks. In this paper, we suggest ...