3693 search results - page 499 / 739 » Splitting a Logic Program |
138
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CSFW
1999
IEEE
15 years 6 months ago
1999
IEEE
Most formal approaches to security protocol analysis are based on a set of assumptions commonly referred to as the "Dolev-Yao model." In this paper, we use a multiset re...
113
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FPGA
1997
ACM
15 years 6 months ago
1997
ACM
We present a general approach to the FPGA technology mapping problem that applies to any logic block composed of lookup tables LUTs and can yield optimal solutions. The connecti...
104
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ISAAC
1992
Springer
15 years 6 months ago
1992
Springer
In the multilevel generalized assignment problem (MGAP) agents can perform tasks at more than one efficiency level. Important manufacturing problems, such as lot sizing, can be ea...
107
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FPGA
2006
ACM
15 years 6 months ago
2006
ACM
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
143
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SPIN
2000
Springer
15 years 6 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...