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ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
14 years 7 months ago
On-chip interconnect modeling by wire duplication
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
IJCNN
2006
IEEE
14 years 4 months ago
Tristability in Model Neurons
— The tristability that a class of two-dimensional neuron models may exhibit is investigated in this paper. One proposition and three corollaries on saddles, which play an import...
Guang-Hong Wang, Ping Jiang
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
14 years 7 months ago
Parameterized model order reduction via a two-directional Arnoldi process
Abstract—This paper presents a multiparameter momentmatching based model order reduction technique for parameterized interconnect networks via a novel two-directional Arnoldi pro...
Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng
ASPDAC
2008
ACM
99views Hardware» more  ASPDAC 2008»
14 years 2 days ago
A delay model for interconnect trees based on ABCD matrix
- The accuracy of interconnect delay estimations can be improved by the method presented in this paper in which the first two moments are obtained with ABCD matrix and a stable mod...
Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng
AUTOMATICA
2007
68views more  AUTOMATICA 2007»
13 years 10 months ago
Frequency domain maximum likelihood estimation of linear dynamic errors-in-variables models
- This paper studies the linear dynamic errors-in-variables problem in the frequency domain. First the identifiability is shown under relaxed conditions. Next a frequency domain Ga...
Rik Pintelon, Johan Schoukens