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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 11 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
ICIP
2009
IEEE
15 years 2 months ago
Randomness-in-Structured Ensembles for compressed sensing of images
Leading compressed sensing (CS) methods require m = O (k log(n)) compressive samples to perfectly reconstruct a k-sparse signal x of size n using random projection matrices (e.g., ...
Abdolreza A. Moghadam, Hayder Radha
174
Voted
PROMISE
2010
14 years 11 months ago
Defect cost flow model: a Bayesian network for predicting defect correction effort
Background. Software defect prediction has been one of the central topics of software engineering. Predicted defect counts have been used mainly to assess software quality and est...
Thomas Schulz, Lukasz Radlinski, Thomas Gorges, Wo...
158
Voted
CASES
2006
ACM
15 years 8 months ago
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
Jason A. Blome, Shantanu Gupta, Shuguang Feng, Sco...
148
Voted
CASES
2005
ACM
15 years 6 months ago
SECA: security-enhanced communication architecture
In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) communication architecture (the fabric that integrates system components and carries the comm...
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Sri...