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» State Space Reduction Techniques for Component Interfaces
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TASE
2007
IEEE
14 years 4 months ago
Symmetry Reduced Model Checking for B
Symmetry reduction is a technique that can help alleviate the problem of state space explosion in model checking. The idea is to verify only a subset of states from each class (or...
Edd Turner, Michael Leuschel, Corinna Spermann, Mi...
CASES
2005
ACM
13 years 11 months ago
Optimizing stream programs using linear state space analysis
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
Sitij Agrawal, William Thies, Saman P. Amarasinghe
ASM
2010
ASM
14 years 1 months ago
A Refinement-Based Correctness Proof of Symmetry Reduced Model Checking
Symmetry reduction is a model checking technique that can help alleviate the problem of state space explosion, by preventing redundant state space exploration. In previous work, we...
Edd Turner, Michael J. Butler, Michael Leuschel
SPIN
2009
Springer
14 years 4 months ago
Fast, All-Purpose State Storage
Existing techniques for approximate storage of visited states in a model checker are too special-purpose and too DRAM-intensive. Bitstate hashing, based on Bloom filters, is good ...
Peter C. Dillinger, Panagiotis Manolios
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
14 years 4 months ago
A formal approach to design space exploration of protocol converters
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
Karin Avnit, Arcot Sowmya