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» State machine models of timing and circuit design
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ICCAD
2006
IEEE
100views Hardware» more  ICCAD 2006»
14 years 4 months ago
Faster, parametric trajectory-based macromodels via localized linear reductions
— Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macromodels for custom circuits. These models are generated by sampling the stat...
Saurabh K. Tiwary, Rob A. Rutenbar
WWW
2005
ACM
14 years 1 months ago
Improved timing control for web server systems using internal state information
How to effectively allocate system resource to meet the Service Level Agreement (SLA) of Web servers is a challenging problem. In this paper, we propose an improved scheme for aut...
Xue Liu, Rong Zheng, Jin Heo, Lui Sha
FMCAD
2004
Springer
14 years 1 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi
NIPS
2000
13 years 9 months ago
Processing of Time Series by Neural Circuits with Biologically Realistic Synaptic Dynamics
Experimental data show that biological synapses behave quite differently from the symbolic synapses in common artificial neural network models. Biological synapses are dynamic, i....
Thomas Natschläger, Wolfgang Maass, Eduardo D...
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 12 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee