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» State machine models of timing and circuit design
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CAV
2000
Springer
197views Hardware» more  CAV 2000»
14 years 2 days ago
Bounded Model Construction for Monadic Second-Order Logics
Address: Abstraction, Composition, Symmetry, and a Little Deduction: The Remedies to State Explosion . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A. Pnueli Invited Address...
Abdelwaheb Ayari, David A. Basin
ISCAS
2003
IEEE
153views Hardware» more  ISCAS 2003»
14 years 1 months ago
A VLSI model of range-tuned neurons in the bat echolocation system
The neural computations that support bat echolocation are of great interest to both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the ...
Matthew Cheely, Timothy K. Horiuchi
ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
14 years 4 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
IFIP
1992
Springer
13 years 11 months ago
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required
This paper presents a completely systematic design procedure for asynchronous controllers. The initial step is the construction of a signal transition graph (STG, an interpreted P...
Jochen Beister, Ralf Wollowski
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 28 days ago
A TCP/IP Based Multi-device Programming Circuit
This paper describes a lightweight Field Programmable Gate Array (FPGA) circuit design that supports the simultaneous programming of multiple devices at different locations throug...
David V. Schuehler, Harvey Ku, John W. Lockwood