1186 search results - page 43 / 238 » State machine models of timing and circuit design |
ASPDAC
2008
ACM
13 years 11 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
ECML
2005
Springer
14 years 2 months ago
2005
Springer
We propose in this paper a novel approach to the induction of the structure of Hidden Markov Models. The induced model is seen as a lumped process of a Markov chain. It is construc...
CORR
2006
Springer
13 years 9 months ago
2006
Springer
The asynchronous systems f are the models of the asynchronous circuits from digital electrical engineering. They are multi-valued functions that associate to each input u : R {0, ...
TCAD
2008
13 years 8 months ago
2008
Abstract--Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and d...
DAC
2003
ACM
14 years 2 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...