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» State machine models of timing and circuit design
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ASM
2005
ASM
14 years 1 months ago
Time in State Machines
State machines are considered a very general means of expressing computations in an implementation-independent way. There are also ways to extend the general state machine framewor...
Susanne Graf, Andreas Prinz
SPIN
2005
Springer
14 years 1 months ago
Model Checking Machine Code with the GNU Debugger
Embedded software verification is an important verification problem that requires the ability to reason about the timed semantics of concurrent behaviors at a low level of atomic...
Eric Mercer, Michael Jones
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
13 years 12 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
DATE
2000
IEEE
121views Hardware» more  DATE 2000»
14 years 1 days ago
Functional Test Generation for Full Scan Circuits
We study the effectiveness of functional tests for full scan circuits. Functional tests are important for design validation, and they potentially have a high defect coverage indep...
Irith Pomeranz, Sudhakar M. Reddy
PG
2003
IEEE
14 years 27 days ago
A State Machine for Real-Time Cutting of Tetrahedral Meshes
We introduce an algorithm that consistently and accurately processes arbitrary intersections in tetrahedral meshes in real-time. The intersection surfaces are modeled up to the cu...
Daniel Bielser, Pascal Glardon, Matthias Teschner,...