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ARC
2010
Springer
167views Hardware» more  ARC 2010»
13 years 10 months ago
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
Kunjan Patel, Chris J. Bleakley
DASIP
2010
13 years 1 months ago
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation
This paper proposes an automatic design flow from userfriendly design to efficient implementation of video processing systems. This design flow starts with the use of coarsegrain ...
Ruirui Gu, Jonathan Piat, Mickaël Raulet, J&o...
AHS
2007
IEEE
211views Hardware» more  AHS 2007»
13 years 10 months ago
Synthesis of Multimode digital signal processing systems
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
Caaliph Andriamisaina, Emmanuel Casseau, Philippe ...
OSDI
2006
ACM
14 years 7 months ago
Securing Software by Enforcing Data-flow Integrity
Software attacks often subvert the intended data-flow in a vulnerable program. For example, attackers exploit buffer overflows and format string vulnerabilities to write data to u...
Manuel Costa, Miguel Castro, Timothy L. Harris
HPCN
2000
Springer
13 years 10 months ago
Data Futures in DISCWorld
Data futures in a metacomputing system refer to data products that have not yet been created but which can be uniquely named and manipulated. We employ data flow mechanisms expres...
Heath A. James, Kenneth A. Hawick