328 search results - page 51 / 66 » Static performance prediction of skeletal parallel programs |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
IPPS
1996
IEEE
13 years 11 months ago
1996
IEEE
Programming distributed-memory machines requires careful placement of datato balance the computationalload among the nodes and minimize excess data movement between the nodes. Mos...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
As bioinformatics is an emerging application of high performance computing, this paper first evaluates the memory performance of several representative bioinformatics application...
VEE
2006
ACM
14 years 1 months ago
2006
ACM
We present Vector LLVA, a virtual instruction set architecture (VISA) that exposes extensive static information about vector parallelism while avoiding the use of hardware-speci...