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» Static timing analysis for modeling QoS in networks-on-chip
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EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
13 years 11 months ago
VHDL quality: synthesizability, complexity and efficiency evaluation
With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintain...
M. Mastretti
ECRTS
2006
IEEE
14 years 1 months ago
Real-Time Memory Management: Life and Times
As real-time and embedded systems become increasingly large and complex, the traditional strictly static approach to memory management begins to prove untenable. The challenge is ...
Andrew Borg, Andy J. Wellings, Christopher D. Gill...
ECRTS
2003
IEEE
14 years 28 days ago
Establishing Timing Requirements and Control Attributes for Control Loops in Real-Time Systems
Advances in scheduling theory have given designers of control systems greater flexibility over their choice of timing requirements. This could lead to systems becoming more respon...
Iain Bate, Peter Nightingale, Anton Cervin
BMCBI
2011
12 years 11 months ago
A Simple Approach to Ranking Differentially Expressed Gene Expression Time Courses through Gaussian Process Regression
Background: The analysis of gene expression from time series underpins many biological studies. Two basic forms of analysis recur for data of this type: removing inactive (quiet) ...
Alfredo A. Kalaitzis, Neil D. Lawrence
WORDS
2005
IEEE
14 years 1 months ago
Towards a Flow Analysis for Embedded System C Programs
Reliable program Worst-Case Execution Time (WCET) estimates are a key component when designing and verifying real-time systems. One way to derive such estimates is by static WCET ...
Jan Gustafsson, Andreas Ermedahl, Björn Lispe...