VHDL quality: synthesizability, complexity and efficiency evaluation

With VHDL models increasing their size, it becomes more important to assure the quality of these descriptions in order to improve simulation performances, to make project maintainability easier and to create an efficient link with hardware synthesis results. Goal of this paper is to summarize the activities carried out within the SAVE project, leading to the development of a collection of static analysis tools in order to reduce the time spent in the design verification phase, to improve modifiability, reusability and readability of models and focusing on the different aspects related to hardware semantics ( synthesizability analysis ).

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: M. Mastretti
• Keywords: Design Verification Phase, EURODAC 1995, Static Analysis Tools, VHDL, VHDL Models