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» Statistical gate sizing for timing yield optimization
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COMCOM
2010
116views more  COMCOM 2010»
13 years 7 months ago
Optimal frame size analysis for framed slotted ALOHA based RFID networks
We offer an analytical solution for the optimal frame size of the non-muting version of the Basic Frame Slotted ALOHA collision resolution protocol for RFID networks. Previous inv...
Zornitza Genova Prodanoff
BMCBI
2007
233views more  BMCBI 2007»
13 years 7 months ago
160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)
Background: To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching s...
Isaac T. S. Li, Warren Shum, Kevin Truong
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
13 years 12 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 4 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
ICCAD
2006
IEEE
103views Hardware» more  ICCAD 2006»
14 years 4 months ago
A statistical framework for post-silicon tuning through body bias clustering
Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constrai...
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaau...