246 search results - page 23 / 50 » Statistical gate sizing for timing yield optimization |
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
JAVA
1999
Springer
13 years 12 months ago
1999
Springer
The Java language incurs a runtime overhead for exception checks and object accesses without an interior pointer in order to ensure safety. It also requires type inclusion test, d...
CORR
2011
Springer
13 years 2 months ago
2011
Springer
Many statistical M-estimators are based on convex optimization problems formed by the weighted sum of a loss function with a norm-based regularizer. We analyze the convergence rat...
KDD
2009
ACM
14 years 8 months ago
2009
ACM
We present a new approach to large-scale graph mining based on so-called backbone refinement classes. The method efficiently mines tree-shaped subgraph descriptors under minimum f...
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...