Sciweavers

246 search results - page 24 / 50
» Statistical gate sizing for timing yield optimization
Sort
View
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 1 months ago
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
Meng-Chiou Wu, Rung-Bin Lin
IPPS
2006
IEEE
14 years 1 months ago
An optimal architecture for a DDC
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...
Tjerk Bijlsma, Pascal T. Wolkotte, Gerard J. M. Sm...
AAAI
2006
13 years 9 months ago
When a Decision Tree Learner Has Plenty of Time
The majority of the existing algorithms for learning decision trees are greedy--a tree is induced top-down, making locally optimal decisions at each node. In most cases, however, ...
Saher Esmeir, Shaul Markovitch
VLSID
2007
IEEE
209views VLSI» more  VLSID 2007»
14 years 8 months ago
Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis
We present minimization methodologies and an algorithm for simultaneous scheduling, binding, and allocation for the reduction of total power and power fluctuation during behaviora...
Saraju P. Mohanty, Elias Kougianos
KDD
2006
ACM
153views Data Mining» more  KDD 2006»
14 years 8 months ago
Spatial scan statistics: approximations and performance study
Spatial scan statistics are used to determine hotspots in spatial data, and are widely used in epidemiology and biosurveillance. In recent years, there has been much effort invest...
Deepak Agarwal, Andrew McGregor, Jeff M. Phillips,...