246 search results - page 39 / 50 » Statistical gate sizing for timing yield optimization |
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
ICDE
2006
IEEE
14 years 9 months ago
2006
IEEE
Database columns are often correlated, so that cardinality estimates computed by assuming independence often lead to a poor choice of query plan by the optimizer. Multidimensional...
CVPR
2009
IEEE
13 years 11 months ago
2009
IEEE
Fusion of 3D laser radar (LIDAR) imagery and aerial optical imagery is an efficient method for constructing 3D virtual reality models. One difficult aspect of creating such models...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
DOLAP
2003
ACM
14 years 25 days ago
2003
ACM
The normalization of a data cube is the process of choosing an ordering for the attribute values, and the chosen ordering will affect the physical storage of the cube’s data. For...