246 search results - page 43 / 50 » Statistical gate sizing for timing yield optimization |
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
CSB
2005
IEEE
14 years 1 months ago
2005
IEEE
Searching genomes for RNA secondary structure with computational methods has become an important approach to the annotation of non-coding RNAs. However, due to the lack of effici...
ICSE
2005
IEEE-ACM
14 years 7 months ago
2005
IEEE-ACM
Greedy algorithms for the construction of software interaction test suites are studied. A framework is developed to evaluate a large class of greedy methods that build suites one ...
PG
2007
IEEE
14 years 1 months ago
2007
IEEE
Interactive animation systems often use a level-of-detail (LOD) control to reduce the computational cost by eliminating unperceivable details of the scene. Most methods employ a m...
SIGMOD
2005
ACM
14 years 7 months ago
2005
ACM
We consider the problem of joining data streams using limited cache memory, with the goal of producing as many result tuples as possible from the cache. Many cache replacement heu...