Abstract. This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results usin...
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, function...
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, ...
This work focuses on the visual representation of relations towards aiding the exploration and analysis of network intrusions. Fundamentally, the visual representations aid an ana...
We solve a longstanding problem by providing a denotational model for nondeterministic programs that identifies two programs iff they have the same range of possible behaviours. W...
We present an application of formal concept analysis aimed at representing a meaningful structure of knowledge communities in the form of a lattice-based taxonomy. The taxonomy gr...
Camille Roth, Sergei A. Obiedkov, Derrick G. Kouri...