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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 2 days ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
ICASSP
2011
IEEE
12 years 11 months ago
Nonnegative 3-way tensor factorization via conjugate gradient with globally optimal stepsize
This paper deals with the minimal polyadic decomposition (also known as canonical decomposition or Parafac) of a 3way array, assuming each entry is positive. In this case, the low...
Jean-Philip Royer, Pierre Comon, Nadège Thi...
ISSE
2010
13 years 6 months ago
A second look at Faster, Better, Cheaper
“Faster, Better, Cheaper” (FBC) was a systems development methodology used by NASA in the 1990s. While usually a deprecated practice, we find that, with certain caveats, it is...
Oussama El-Rawas, Tim Menzies
PDP
2011
IEEE
12 years 11 months ago
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
Jia Huang, Christian Buckl, Andreas Raabe, Alois K...
CEC
2010
IEEE
13 years 8 months ago
Constrained global optimization of low-thrust interplanetary trajectories
The optimization of spacecraft trajectories can be formulated as a global optimization task. The complexity of the problem depends greatly on the problem formulation, on the spacec...
Chit Hong Yam, David Di Lorenzo, Dario Izzo