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GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
MTV
2003
IEEE
154views Hardware» more  MTV 2003»
14 years 2 months ago
Tuning the VSIDS Decision Heuristic for Bounded Model Checking
Bounded Model Checking (BMC) techniques have been used for formal hardware verification, with the help of tools such as GRASP (Generic search Algorithm for Satisfiability Proble...
Ohad Shacham, Emmanuel Zarpas
CAV
2001
Springer
121views Hardware» more  CAV 2001»
14 years 1 months ago
A Practical Approach to Coverage in Model Checking
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
Hana Chockler, Orna Kupferman, Robert P. Kurshan, ...
FSTTCS
2010
Springer
13 years 7 months ago
Model checking time-constrained scenario-based specifications
We consider the problem of model checking message-passing systems with real-time requirements. As behavioural specifications, we use message sequence charts (MSCs) annotated with ...
S. Akshay, Paul Gastin, Madhavan Mukund, K. Naraya...
RP
2009
Springer
136views Control Systems» more  RP 2009»
14 years 3 months ago
Probabilistic Model Checking of Biological Systems with Uncertain Kinetic Rates
We present an abstraction of the probabilistic semantics of Multiset Rewriting to formally express systems of reactions with uncertain kinetic rates. This allows biological systems...
Roberto Barbuti, Francesca Levi, Paolo Milazzo, Gu...