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DATE
2008
IEEE
112views Hardware» more  DATE 2008»
15 years 11 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
ICML
2007
IEEE
16 years 5 months ago
Robust non-linear dimensionality reduction using successive 1-dimensional Laplacian Eigenmaps
Non-linear dimensionality reduction of noisy data is a challenging problem encountered in a variety of data analysis applications. Recent results in the literature show that spect...
Samuel Gerber, Tolga Tasdizen, Ross T. Whitaker
ICPR
2008
IEEE
16 years 5 months ago
Semi-supervised learning on large complex simulations
Complex simulations can generate very large amounts of data stored disjointly across many local disks. Learning from this data can be problematic due to the difficulty of obtainin...
John Nicholas Korecki, Kevin W. Bowyer, Larry O. H...
DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
15 years 11 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch
ICIP
2009
IEEE
15 years 2 months ago
Expanded bag of words representation for object classification
Currently, the bag of visual words (BOW) representation has received wide applications in object categorization. However, the BOW representation ignores the dependency relationshi...
Tinglin Liu, Jing Liu, Qingshan Liu, Hanqing Lu