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SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
14 years 1 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
HIPEAC
2009
Springer
14 years 2 months ago
Parallel H.264 Decoding on an Embedded Multicore Processor
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inte...
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurli...
DSD
2008
IEEE
104views Hardware» more  DSD 2008»
13 years 7 months ago
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures
Efficient utilization of multi-core architectures relies on the partitioning of applications into tasks and mapping the tasks to cores. In some applications (e.g. H.264 video deco...
Magnus Själander, Andrei Terechko, Marc Duran...
EUROPAR
2009
Springer
13 years 11 months ago
StarPU: A Unified Platform for Task Scheduling on Heterogeneous Multicore Architectures
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
Cédric Augonnet, Samuel Thibault, Raymond N...
IPPS
2010
IEEE
13 years 5 months ago
Ensuring deterministic concurrency through compilation
Abstract--Multicore shared-memory architectures are becoming prevalent but bring many programming challenges. Among the biggest is non-determinism: the output of the program does n...
Nalini Vasudevan, Stephen A. Edwards