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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
14 years 2 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock
QEST
2010
IEEE
13 years 7 months ago
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs
Adaptive techniques like voltage and frequency scaling, process variations and the randomness of input data contribute signi cantly to the statistical aspect of contemporary hardwa...
Jayanand Asok Kumar, Shobha Vasudevan
HPCA
1998
IEEE
14 years 1 months ago
Address Translation Mechanisms In Network Interfaces
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
Ioannis Schoinas, Mark D. Hill
SAC
2010
ACM
14 years 4 months ago
Referrer graph: a low-cost web prediction algorithm
This paper presents the Referrer Graph (RG) web prediction algorithm as a low-cost solution to predict next web user accesses. RG is aimed at being used in a real web system with ...
B. de la Ossa, Ana Pont, Julio Sahuquillo, Jos&eac...
ICC
2007
IEEE
14 years 3 months ago
Optimal Precoder for Rate 1 Space-Time Block Codes
Abstract— Despite primary space-time coding where the channel state information (CSI) is available at the receiver only, the capacity and performance of multiple-input multiple-o...
Alireza Ghaderipoor, Chintha Tellambura