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CHARME
2005
Springer
143views Hardware» more  CHARME 2005»
14 years 2 months ago
Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning
Abstract. We propose a new saturation-based symbolic state-space generation algorithm for finite discrete-state systems. Based on the structure of the high-level model specificat...
Gianfranco Ciardo, Andy Jinqing Yu
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 9 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
CORR
2007
Springer
147views Education» more  CORR 2007»
13 years 9 months ago
Model Checking Synchronized Products of Infinite Transition Systems
Formal verification using the model checking paradigm has to deal with two aspects: The system models are structured, often as products of components, and the specification logic...
Stefan Wöhrle, Wolfgang Thomas
COOPIS
2003
IEEE
14 years 2 months ago
Analysing Mailboxes of Asynchronous Communicating Components
Abstract. Asynchronous communications are prominent in distributed and mobile systems. Often consystems consider an abstract point of view with synchronous communications. However ...
Jean-Claude Royer, Michael Xu
RTCSA
1999
IEEE
14 years 1 months ago
A Symbolic Model Checker for Testing ASTRAL Real-Time Specifications
ASTRAL is a high-level formal specification language for real-time (infinite state) systems. It is provided with structuring mechanisms that allow one to build modularized specifi...
Zhe Dang, Richard A. Kemmerer