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GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
14 years 6 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 6 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
MOBISYS
2011
ACM
14 years 5 months ago
Odessa: enabling interactive perception applications on mobile devices
Resource constrained mobile devices need to leverage computation on nearby servers to run responsive applications that recognize objects, people, or gestures from real-time video....
Moo-Ryong Ra, Anmol Sheth, Lily B. Mummert, Padman...
PODS
2011
ACM
238views Database» more  PODS 2011»
14 years 5 months ago
Beyond simple aggregates: indexing for summary queries
Database queries can be broadly classified into two categories: reporting queries and aggregation queries. The former retrieves a collection of records from the database that mat...
Zhewei Wei, Ke Yi
POPL
2011
ACM
14 years 5 months ago
Dynamic inference of static types for ruby
There have been several efforts to bring static type inference to object-oriented dynamic languages such as Ruby, Python, and Perl. In our experience, however, such type inference...
Jong-hoon (David) An, Avik Chaudhuri, Jeffrey S. F...