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DAC
2008
ACM
14 years 8 months ago
Robust chip-level clock tree synthesis for SOC designs
A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to differ...
Anand Rajaram, David Z. Pan
PODS
2005
ACM
99views Database» more  PODS 2005»
14 years 7 months ago
XML type checking with macro tree transducers
MSO logic on unranked trees has been identified as a convenient theoretical framework for reasoning about expressiveness and implementations of practical XML query languages. As a...
Sebastian Maneth, Alexandru Berlea, Thomas Perst, ...
WEA
2010
Springer
330views Algorithms» more  WEA 2010»
14 years 2 months ago
Exact Bipartite Crossing Minimization under Tree Constraints
A tanglegram consists of a pair of (not necessarily binary) trees T1, T2 with leaf sets L1, L2. Additional edges, called tangles, may connect nodes in L1 with those in L2. The task...
Frank Baumann, Christoph Buchheim, Frauke Liers
IFIP
2004
Springer
14 years 1 months ago
Efficient Protocols for Computing the Optimal Swap Edges of a Shortest Path Tree
We consider the problem of computing the optimal swap edges of a shortest-path tree. This theoretical problem arises in practice in systems that offer point-offailure shortest-path...
Paola Flocchini, Antonio Mesa Enriques, Linda Pagl...
CORR
2007
Springer
165views Education» more  CORR 2007»
13 years 7 months ago
Comparison of Tree-Child Phylogenetic Networks
Abstract—Phylogenetic networks are a generalization of phylogenetic trees that allow for the representation of non-treelike evolutionary events, like recombination, hybridization...
Gabriel Cardona, Francesc Rosselló, Gabriel...