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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
14 years 2 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
14 years 2 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...
PADS
1997
ACM
14 years 2 months ago
The Dark Side of Risk (what your mother never told you about Time Warp)
This paper is a reminder of the danger of allowing \risk" when synchronizing a parallel discrete-event simulation: a simulation code that runs correctly on a serial machine m...
David M. Nicol, X. Liu
SPAA
1997
ACM
14 years 2 months ago
Pipelining with Futures
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
Guy E. Blelloch, Margaret Reid-Miller
EUROCOLT
1997
Springer
14 years 2 months ago
Vapnik-Chervonenkis Dimension of Recurrent Neural Networks
Most of the work on the Vapnik-Chervonenkis dimension of neural networks has been focused on feedforward networks. However, recurrent networks are also widely used in learning app...
Pascal Koiran, Eduardo D. Sontag