198 search results - page 25 / 40 » Supporting Cache Coherence in Heterogeneous Multiprocessor S... |
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
Scalability of applications on distributed sharedmemory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism y...
PVM
1997
Springer
13 years 11 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
TC
2010
13 years 6 months ago
2010
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Hardware transactional memory has great potential to simplify the creation of correct and efficient multithreaded programs, allowing programmers to exploit more effectively the s...
HPCA
1997
IEEE
13 years 12 months ago
1997
IEEE
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...