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ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 28 days ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
WSC
1998
13 years 9 months ago
Marine Corps Analytic Modeling and Simulation
The Marine Corps has instituted a new Mission Area Analysis (MAA) process to identify operational requirements and deficiencies. In the past, the MAA process was subjective and so...
William A. Sawyers
PVLDB
2010
158views more  PVLDB 2010»
13 years 6 months ago
MEET DB2: Automated Database Migration Evaluation
Commercial databases compete for market share, which is composed of not only net-new sales to those purchasing a database for the first time, but also competitive “win-backs”...
Reynold Xin, Patrick Dantressangle, Sam Lightstone...
DRR
2010
13 years 10 months ago
Biomedical article retrieval using multimodal features and image annotations in region-based CBIR
Biomedical images are invaluable in establishing diagnosis, acquiring technical skills, and implementing best practices in many areas of medicine. At present, images needed for in...
Daekeun You, Sameer Antani, Dina Demner-Fushman, M...
ASPLOS
1989
ACM
13 years 11 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....