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CJ
2006
84views more  CJ 2006»
13 years 7 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
SPAA
2009
ACM
14 years 7 months ago
Buffer management for colored packets with deadlines
We consider buffer management of unit packets with deadlines for a multi-port device with reconfiguration overhead. The goal is to maximize the throughput of the device, i.e., the...
Yossi Azar, Uriel Feige, Iftah Gamzu, Thomas Mosci...
KDD
2007
ACM
141views Data Mining» more  KDD 2007»
14 years 7 months ago
Mining favorable facets
The importance of dominance and skyline analysis has been well recognized in multi-criteria decision making applications. Most previous studies assume a fixed order on the attribu...
Raymond Chi-Wing Wong, Jian Pei, Ada Wai-Chee Fu, ...
MICRO
2009
IEEE
315views Hardware» more  MICRO 2009»
14 years 2 months ago
Control flow obfuscation with information flow tracking
Recent micro-architectural research has proposed various schemes to enhance processors with additional tags to track various properties of a program. Such a technique, which is us...
Haibo Chen, Liwei Yuan, Xi Wu, Binyu Zang, Bo Huan...
MIE
2008
128views Healthcare» more  MIE 2008»
13 years 8 months ago
Interface Terminologies: Bridging the Gap between Theory and Reality for Africa
In the United States and Europe, electronic health records (EHRs) allow information technology and decision-support to facilitate the activities of clinicians and are considered a...
Andrew S. Kanter, Amy Y. Wang, Fred E. Masarie Jr....