As the requirements for system analysis and design become more complex, the need for a natural, yet formal way of specifying system analysis findings and design decisions are becom...
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
A detailed connectionist architecture is described which is capable of relating psychological behavior to the functioning of neurons and neurochemicals. The need to be able to bui...
This paper evaluates the performance of the parallel, main-memory DBMS, PRISMA/DB. First, an architecture for parallel query execution is presented. A performance model for the ex...
Annita N. Wilschut, Jan Flokstra, Peter M. G. Aper...
In this paper we propose the Enhanced QoS Border Gateway Protocol1 (EQ-BGP) aimed at performing the inter-domain QoS routing in a multi-domain IP network. The objective of EQ-BGP ...