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» SyCE: An Integrated Environment for System Design in SystemC
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OSDI
2002
ACM
14 years 10 months ago
An Integrated Experimental Environment for Distributed Systems and Networks
Three experimental environments traditionally support network and distributed systems research: network emulators, network simulators, and live networks. The continued use of mult...
Brian White, Jay Lepreau, Leigh Stoller, Robert Ri...
TVLSI
2008
120views more  TVLSI 2008»
13 years 9 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
ECBS
1999
IEEE
171views Hardware» more  ECBS 1999»
14 years 2 months ago
Metamodeling - Rapid Design and Evolution of Domain-Specific Modeling Environments
Model integrated computing (MIC) is gaining increased attention as an effective and efficient method for developing, maintaining, and evolving large-scale, domain-specific softwar...
Greg Nordstrom, Janos Sztipanovits, Gabor Karsai, ...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
14 years 1 months ago
GRAAL - A Development Framework for Embedded Graphics Accelerators
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
CORR
2007
Springer
127views Education» more  CORR 2007»
13 years 9 months ago
Common Reusable Verification Environment for BCA and RTL Models
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
Giuseppe Falconeri, Walid Naifer, Nizar Romdhane