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DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 12 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...
LICS
1998
IEEE
13 years 12 months ago
Existential Second-Order Logic over Strings
d abstract) T. Eiter G. Gottlob Y. Gurevich Institut fur Informatik Institut fur Informationssysteme EECS Department Universitat Gie en Technische Universitat Wien University of Mi...
Thomas Eiter, Georg Gottlob, Yuri Gurevich
ICCTA
2007
IEEE
13 years 11 months ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
ACSD
2004
IEEE
118views Hardware» more  ACSD 2004»
13 years 11 months ago
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments
Abstract. A delay-insensitive module communicates with its environment through wires of unbounded delay. To avoid transmission interference, the absorption of a signal transition m...
Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Fur...
CSFW
2004
IEEE
13 years 11 months ago
Modelling Downgrading in Information Flow Security
Information flow security properties such as noninterference ensure the protection of confidential data by strongly limiting the flow of sensitive information. However, to deal wi...
Annalisa Bossi, Carla Piazza, Sabina Rossi