788 search results - page 60 / 158 » Symbolic Equivalence Checking |
SAS
2007
Springer
14 years 2 months ago
2007
Springer
Interval analysis seeks static lower and upper bounds on the values of program variables. These bounds are useful, especially for inferring invariants to prove buffer overflow ch...
MMB
2010
Springer
13 years 9 months ago
2010
Springer
Abstract. Bisimulation reduction is a classical means to fight the infamous state space explosion problem, which limits the applicability of automated methods for verification li...
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
— With the success of formal verification techniques like equivalence checking and model checking for hardware designs, there has been growing interest in applying such techniqu...
ATVA
2007
Springer
14 years 2 months ago
2007
Springer
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
TACAS
2001
Springer
14 years 8 days ago
2001
Springer
Multi-valued logics support the explicit modeling of uncertainty and disagreement by allowing additional truth values in the logic. Such logics can be used for verification of dyn...