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ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 28 days ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
CORR
2009
Springer
74views Education» more  CORR 2009»
13 years 5 months ago
Parallelizing Deadlock Resolution in Symbolic Synthesis of Distributed Programs
Previous work has shown that there are two major complexity barriers in the synthesis of fault-tolerant distributed programs, namely generation of fault-span, the set of states re...
Fuad Abujarad, Borzoo Bonakdarpour, Sandeep S. Kul...
DSN
2007
IEEE
13 years 11 months ago
Determining Fault Tolerance of XOR-Based Erasure Codes Efficiently
We propose a new fault tolerance metric for XOR-based erasure codes: the minimal erasures list (MEL). A minimal erasure is a set of erasures that leads to irrecoverable data loss ...
Jay J. Wylie, Ram Swaminathan
PRDC
1999
IEEE
13 years 12 months ago
Cost of Ensuring Safety in Distributed Database Management Systems
Generally, applications employing Database Management Systems (DBMS) require that the integrity of the data stored in the database be preserved during normal operation as well as ...
Maitrayi Sabaratnam, Svein-Olaf Hvasshovd, Ø...
TCAD
2002
106views more  TCAD 2002»
13 years 7 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...