321 search results - page 22 / 65 » Symbolic Model Checking for Probabilistic Timed Automata |
ASWEC
2007
IEEE
14 years 3 months ago
2007
IEEE
Behavior Trees (BTs) are a graphical notation used for formalising functional requirements and have been successfully applied to several case studies. However, the notation curren...
HYBRID
1995
Springer
14 years 8 days ago
1995
Springer
Uppaal is a new tool suit for automatic veri cation of networks of timed automata. In this paper we describe the diagnostic model-checking feature of Uppaal and illustrates its use...
FORMATS
2004
Springer
14 years 2 months ago
2004
Springer
For successful software verification, model checkers must be capable of handling a large number of program variables. Traditional, BDD-based model checking is deficient in this reg...
ASPDAC
2007
ACM
14 years 22 days ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
FORMATS
2004
Springer
14 years 14 days ago
2004
Springer
We discuss the modeling and verification of real-time systems using the SAL model checker. A new modeling framework based on event calendars enables dense timed systems to be descr...