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» Symbolic Model Checking for Probabilistic Timed Automata
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IEICET
2006
114views more  IEICET 2006»
13 years 7 months ago
Synchronization Verification in System-Level Design with ILP Solvers
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro ...
ADAEUROPE
2005
Springer
14 years 1 months ago
Non-intrusive System Level Fault-Tolerance
This paper describes the methodology used to add nonintrusive system-level fault tolerance to an electronic throttle controller. The original model of the throttle controller is a...
Kristina Lundqvist, Jayakanth Srinivasan, Sé...
ACSD
2006
IEEE
81views Hardware» more  ACSD 2006»
14 years 1 months ago
Monitoring and fault-diagnosis with digital clocks
We study the monitoring and fault-diagnosis problems for dense-time real-time systems, where observers (monitors and diagnosers) have access to digital rather than analog clocks. ...
Karine Altisen, Franck Cassez, Stavros Tripakis
AAAI
2006
13 years 8 months ago
DNNF-based Belief State Estimation
As embedded systems grow increasingly complex, there is a pressing need for diagnosing and monitoring capabilities that estimate the system state robustly. This paper is based on ...
Paul Elliott, Brian C. Williams
SPIN
2000
Springer
13 years 11 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader