43 search results - page 8 / 9 » Symbolic Model Checking of Analog Mixed-Signal Circuits |
TPHOL
1999
IEEE
13 years 12 months ago
1999
IEEE
Combining theorem proving and model checking o ers the tantalizing possibility of e ciently reasoning about large circuits at high levels of abstraction. We have constructed a syst...
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
FMCAD
2004
Springer
14 years 1 months ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
ng Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation Yan Chen Dept. of Computer Science Portland State University Portland, OR, 97207 chenyan@cs.pdx.e...
ASYNC
1997
IEEE
13 years 11 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...