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ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
13 years 11 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
SPIN
2000
Springer
13 years 11 months ago
Verification and Optimization of a PLC Control Schedule
Abstract. We report on the use of model checking techniques for both the verification of a process control program and the derivation of optimal control schedules. Most of this wor...
Ed Brinksma, Angelika Mader
POPL
2005
ACM
14 years 8 months ago
Synthesis of interface specifications for Java classes
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
P. Madhusudan, Pavol Cerný, Rajeev Alur, Wo...
TACAS
2005
Springer
124views Algorithms» more  TACAS 2005»
14 years 1 months ago
Dynamic Symmetry Reduction
Abstract. Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the proh...
E. Allen Emerson, Thomas Wahl
AAAI
2008
13 years 10 months ago
Optimal Metric Planning with State Sets in Automata Representation
This paper proposes an optimal approach to infinite-state action planning exploiting automata theory. State sets and actions are characterized by Presburger formulas and represent...
Björn Ulrich Borowsky, Stefan Edelkamp