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» Symbolic timing simulation using cluster scheduling
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GLOBECOM
2006
IEEE
14 years 4 months ago
High-rate, Double-Symbol-Decodable STBCs from Clifford Algebras
— For the number of transmit antennas N = 2a the maximum rate (in complex symbols per channel use) of all the Quasi-Orthogonal Designs (QODs) reported in the literature is a 2a...
Sanjay Karmakar, B. Sundar Rajan
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 3 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
14 years 4 months ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch
TRIDENTCOM
2005
IEEE
14 years 3 months ago
Integrated Network Experimentation using Simulation and Emulation
Discrete-event packet-level network simulation is well-known and widely used. Network emulation is a hybrid approach that combines real elements of a deployed networked applicatio...
Shashi Guruprasad, Robert Ricci, Jay Lepreau
EUROPAR
2009
Springer
14 years 4 months ago
Steady-State for Batches of Identical Task Trees
Abstract In this paper, we focus on the problem of scheduling batches of identical task graphs on a heterogeneous platform, when the task graph consists in a tree. We rely on stead...
Sékou Diakité, Loris Marchal, Jean-M...