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IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
ATS
2009
IEEE
127views Hardware» more  ATS 2009»
14 years 22 days ago
On the Generation of Functional Test Programs for the Cache Replacement Logic
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá...
MSS
2000
IEEE
89views Hardware» more  MSS 2000»
14 years 21 hour ago
Access Coordination of Tertiary Storage for High Energy Physics Applications
We describe a real implementation of a software component that manages caching of files from a tertiary storage management system to a large disk cache developed for use in the a...
Luis M. Bernardo, Arie Shoshani, Alex Sim, Henrik ...
SIGCOMM
1998
ACM
13 years 12 months ago
Improving End-to-End Performance of the Web Using Server Volumes and Proxy Filters
The rapid growth of the World Wide Web has caused serious performance degradation on the Internet. This paper o ers an end-to-end approach to improving Web performance by collecti...
Edith Cohen, Balachander Krishnamurthy, Jennifer R...
ICPP
2009
IEEE
14 years 2 months ago
Bank-aware Dynamic Cache Partitioning for Multicore Architectures
Abstract—As Chip-Multiprocessor systems (CMP) have become the predominant topology for leading microprocessors, critical components of the system are now integrated on a single c...
Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. Joh...