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» Synapses as dynamic memory buffers
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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
13 years 12 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
CASCON
2008
106views Education» more  CASCON 2008»
13 years 8 months ago
Using economic models to allocate resources in database management systems
Resource allocation in database management systems is a performance management process in which an autonomic DBMS makes resource allocation decisions based on properties like work...
Mingyi Zhang, Patrick Martin, Wendy Powley, Paul B...
TPDS
2010
260views more  TPDS 2010»
13 years 5 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
EUROSYS
2009
ACM
14 years 3 months ago
Pointless tainting?: evaluating the practicality of pointer tainting
This paper evaluates pointer tainting, an incarnation of Dynamic Information Flow Tracking (DIFT), which has recently become an important technique in system security. Pointer tai...
Asia Slowinska, Herbert Bos
DSN
2005
IEEE
14 years 6 days ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh